1. Field
Various features relate to physically unclonable functions (PUFs), and in particular to PUFs based on the breakdown voltages of an array of metal-insulator-metal devices, such as magnetoresistive random-access memory (MRAM) cells.
2. Background
An on-chip PUF is a chip-unique challenge-response mechanism exploiting manufacturing process variations inside integrated circuits (ICs). When a physical stimulus (i.e., challenge) is applied to the PUF, the PUF generates a response in an unpredictable but repeatable way due to the complex interaction of the stimulus with the physical microstructure of the device employing the PUF. This exact microstructure depends on physical factors introduced during manufacture of the device employing the PUF, which are unpredictable. The PUF's “unclonability” means that each device employing the PUF has a unique and unpredictable way of mapping challenges to responses, even if one device is manufactured with the same process as another seemingly identical device. Thus, it is practically infeasible to construct a PUF with the same challenge-response behavior as another device's PUF because exact control over the manufacturing process is infeasible.
FIG. 1 illustrates a metal-insulator-metal (MIM) device 100 found in the prior art. The MIM device 100 includes a first metal layer 102, a second metal layer 104, and an insulator layer 106 positioned between the first and second metal layers 102, 104. If the insulator layer 106 is thin enough and a voltage level VF applied between the first and second metal layers 102, 104 (i.e., across the insulator layer 106) exceeds a certain threshold value, then the insulator layer 106 may breakdown and conductive “pin holes” (not shown) may form within the insulator layer 106. The conductive pin holes electrically couple the first and second metal layers 102, 104 and significantly lower the resistance between the metal layers 102, 104. Typically, this breakdown and pin hole formation is irreversible. The minimum voltage level applied between the first and second metal layers 102, 104 that causes breakdown of the insulator layer 106 may be referred to herein as the breakdown voltage VBR.
MRAM is a non-volatile random-access memory that, unlike conventional RAM, stores data not as electric charge but instead as electron spin within magnetic storage elements. FIG. 2 illustrates a schematic diagram of at least a portion of a spin transfer torque (STT) MRAM circuit cell 200 found in the prior art. The MRAM cell 200 includes a free layer 202, a reference layer (also known as “pinned reference layer”) 204, a tunnel junction layer 206, and an anti-ferromagnetic (AFM) pinning layer 208. The free layer 202 is a ferromagnetic layer whose magnetic polarity is not fixed but is instead free to change direction in response to an external magnetic field (not shown). The reference layer 204 includes a first ferromagnetic layer 205 and a second ferromagnetic layer 207 that have opposite magnetic polarities. By contrast to the free layer 202, the reference layer 204 has a magnetic polarity that is fixed such that the magnetic polarities of the first and second ferromagnetic layers 205, 207 do not change direction in the presence of the aforementioned external magnetic field. The AFM pinning layer 208 is an anti-ferromagnetic layer that controls the magnetic polarities of the reference layer 206.
Situated in between the free layer 202 and the reference layer's first ferromagnetic layer 204 is the tunnel junction layer 206. The tunnel junction layer 206 is made of a very thin insulating material, such as magnesium oxide (MgO). The tunnel junction layer 206 is so thin that electrons may actually flow through (e.g., tunnel through) the layer 206 despite the layer 206 being an insulator. In most prior art MRAM applications the magnetic polarity direction of the free layer 202 relative to the first ferromagnetic layer 205 (e.g., parallel to each other or antiparallel to each other) represents one of two different logical data bit states (e.g. data bit “1” or data bit “0”).
A signal line voltage VSL applied to the MRAM cell 200 controls the flow of current ISL through the MRAM cell 200. For example, applying a positive voltage VSL that exceeds the transition voltage VT of the cell 200 causes the current ISL to flow in the direction shown in FIG. 2 and also causes the magnetic polarity of the free layer 202 to change direction (e.g., from being parallel to the first ferromagnetic layer's 205 magnetic polarity to being antiparallel). To change the magnetic polarity direction of the free layer 202 back, a negative signal line voltage VSL that exceeds VT (e.g., the ground and VSL terminals in FIG. 2 are reversed) is applied to cause the current ISL to flow in the opposite direction shown in FIG. 2.
Notably, if the signal line voltage VSL causes the voltage differential between the two surfaces 211, 213 of the tunnel junction layer 206 to exceed a threshold voltage, then the tunnel junction layer 206 breaks down and conductive pin holes are formed within the thin insulating layer 206. The signal line voltage VSL that causes the tunnel junction layer 206 to breakdown may also be referred to herein as the breakdown voltage VBR. The conductive pin holes (not shown) that pass through the thickness of the tunnel junction layer 206 cause the resistance of the tunnel junction layer 206 to significantly drop. Typically, a broken down tunnel junction layer 206 is permanent and the pin holes formed cannot be reversed/removed. The breakdown voltage VBR of the MRAM cell 200 should be greater than the transition voltage VT of the cell 200.
There exists a need for methods and apparatuses that implement PUFs based on metal-insulator-metal (MIM) devices having thin insulating layers, such as MRAM circuit cells. Specifically, there exists a need to implement PUFs based on the random breakdown voltage VBR variation among a plurality of MIMs within a MIM array, such as MRAM cells within an MRAM cell array. Such MIM and/or MRAM based PUFs may provide a secure means to uniquely identify electronic devices, such as integrated circuits, and/or provide secure cryptographic keys for cryptographic security algorithms.